Battery operated devices are widely used. For example, many patients can benefit from wearable medical devices that provide real-time monitoring and possibly on-site treatment. It is desirable for such devices to operate under a single micro battery that is lightweight and low-volume. Therefore, such devices require operating at a low supply voltage (e.g. 1-1.5V) with ultra low power consumption for long battery lifetime. In addition, the devices also need to exhibit low input referred noise in order to pick up very weak biomedical signals. It is also desirable for such devices to have rail-rail input range. As such, a low voltage low power biomedical signal acquisition integrated circuit (IC) is required.
The analog-to-digital converter (ADC) serves as the interface between real world parameters and digital circuits and is an important component in a mixed-signal IC. It is important that the ADC is of low voltage and low power. Successive approximation ADC based on charge redistribution has been widely used in low power applications. Its operation principle is the same binary-search algorithm used in all successive approximation ADCs.
FIG. 1 shows a conventional successive approximation ADC 100 based on charge redistribution. The binary-weighted capacitor array 102 of the ADC 100 acts as both a digital-to-analog converter (DAC) and a sample capacitor. The conventional ADC 100 relies heavily on analog CMOS switches, which should pass analog signals of all levels to the capacitor array 102. However, at low supply voltages, i.e. VDD<Vthn+Vthp, the CMOS switches will exhibit very high impedance for signals near half of VDD. Thus, the conventional ADC 100 is not suitable for low-voltage operation. Several modifications have been proposed to reduce the supply voltage.
For example, a structure of an ADC 200 where the input is directly fed to a comparator 202, as shown in FIG. 2, has been proposed. The switches that control the capacitor array are only required to pass supply-rail-level signals since they are no longer connected to the input signal. However, noting the existence of a sample-and-hold (S/H) circuit 204 at the input of the comparator 202, potential problems may still exist for the switches. The remedy here is to scale the DAC output to only half of VDD or lower to allow the correct operation of the S/H circuit 204. Although this structure 200 can work under low supply voltage (i.e. VDD<Vthn+Vthp), its input range is limited to the common-mode input range or half of VDD, whichever is the lower. Thus, it cannot handle rail-rail input signal.
Further, a structure that does not require the comparator to have a wide common-mode input range has also been proposed. However, it needs an extra capacitor in addition to the capacitor array, which increases costs.
FIG. 3 shows a structure of an ADC 300 where rail-rail input range is achieved by scaling down the input signal prior to conversion. The signal scaling is performed by using an extra capacitor, which increases cost.
A S/H circuit usually precedes an ADC and consumes a non-negligible amount of power and chip area. Although it is possible to combine the S/H circuit and the comparator to save chip area, additional power consumption is still needed to provide the S/H function.
Therefore, there is a need to provide an ADC for low voltage and low power operation with rail-rail input range to address at least one of the above-mentioned problems.